1. Field of the Invention
The present invention relates to a process for the production of a semiconductor device. More particularly, the present invention relates to a method of forming an electrically insulating layer, i.e., dielectric layer, between metal or other electrically conducting layers in the semiconductor device. The dielectric layer is referred hereinafter to as an interlayer dielectric layer. Also, the dielectric layer can act as a protective layer for protecting the device from the environment, if it is applied to the top surface of the device.
As is appreciated from the following descriptions of the present invention, the term "semiconductor device" used herein is intended to mean a variety of devices having a substrate consisting of semiconductor material, such as semiconductor integrated circuits (ICs), large-scale-integration circuits (LSIs), very-large-scale-integration circuits (VLSIs), ultra-large-scale-integration circuits (ULSIs) and the like as well as other electronic devices using semiconductor material.
2. Description of the Related Art
In recent years, the integration of the semiconductor devices has been surprisingly advanced for the purpose of attaining rapid processing of voluminous information. The LSI and VLSI circuits are commercially worked, and further the ULSI circuits will be worked soon. Note that the advances in the integration do not rely upon the expansion of the size or dimension of the device, i.e., chip, but, can be attained by miniaturizing and increasing of components to be fabricated in the chip and accordingly reducing the dimension of the chips. As a result, the minimum size of line and space of the wiring in the chips is on the order of submicrons and as a necessity, the wiring structure adopted in recent chips is a multilayer or multilevel wiring or metallization structure.
In the prior art production of integrated semiconductor devices, fine patterns of semiconductor regions, electrodes, wiring and other components are fabricated onto the semiconductor substrate by using conventional process steps such as ion implantation of impurities, thin film deposition and photolithography. The thus resulting patterned wiring layer contains a plurality of fine topographic features (projections and depressions) and steps.
After formation thereof, an interlayer dielectric layer is formed over the patterned wiring layer, and then via-holes or through-holes are bored in the predetermined sites of the dielectric layer. The next wiring layer is deposited and patterned over the dielectric layer, and the upper and lower wiring layers are electrically connected by using the above-mentioned process steps. The desired integrated semiconductor device is thus provided.
The dielectric layer sandwiched between two patterned wiring layers must to satisfy the following requirements:
1. It should show an excellent dielectric property, i.e., electrical insulating property. PA1 2. It should show a good resistance to heat. PA1 3. It should have a smooth surface, namely, it should show good planarization. PA1 4. It should show a good resistance to cracking. PA1 R.sub.2 represents a substituted or unsubstituted methylene or methyn group; and PA1 m and n each is a positive integer satisfying the condition of 10&lt;m+n&lt;1000 and a ratio of n and m is less than 0.3(n/m&lt;0.3), in a solvent onto a substrate having electrically conductive components fabricated therein, and curing the coated layer of the polycarbosilane at a temperature of not less than 350.degree. C. in an oxidizing atmosphere to thereby convert the polycarbosilane layer to a silicon oxide layer.
A plurality of dielectric materials have been proposed for use as interlayer dielectric layers, however, none of them is considered to be sufficiently satisfy all the above-mentioned requirements. The dielectric layer-forming materials include both inorganic and organic dielectric materials, and they are applied over the wiring layer by a chemical vapour deposition (CVD) process, sputtering process or spin-coating process, for example.
Typical examples of useful inorganic dielectric materials include silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4) and phosphosilicate glass (PSG). The dielectric layer formed from these inorganic materials exhibits an excellent dielectric property and resistance to heat, however, if it is formed by thin film deposition technology such as CVD or sputtering process, the dielectric layer suffers from unevenness of the surface and thus disconnection of the wiring, because it can exactly reproduce an uneven and stepped profile of the underlying wiring layer.
On the other hand, typical examples of useful organic dielectric materials include polyimide resins and so-called "organic SOG (spin-on-glass)". The polyimide resins, particularly, recently developed photo-sensitive polyimide resins are useful in view of their good workability, because they can be subjected to a photolithographic process without using a resist material as a patterned mask. However, due to presence of imide rings having a higher polarity in the molecular structure thereof, the polyimide resins show a higher hygroscopicity or moisture absorption, and thus cause a problem that a dielectric property of the resulting layer is lowered as a result of an increase of the apparent dielectric constant which increase with moisture adsorption.
The SOG materials are those produced from silicon alkoxide of the formula: Si(OR).sub.4 wherein R represents an alkyl group, which is then hydrolyzed to provide the following equilibrium condition of the reaction: EQU Si(OR).sub.4 +4H.sub.2 O=Si(OH).sub.n (OR).sub.4-n +nROH
Using the SOG materials, it is possible to provide a thick dielectric layer having a smooth surface, because they can be spin-coated, and the dielectric property and heat resistance of the resulting layer are not so high as those of the above-mentioned inorganic dielectric materials, but are sufficiently high for practical use. However, the SOG layer suffers from formation of fine pores and cracking. Namely, upon heating of the SOG layer coated over the substrate, the hydroxyl (OH) groups constituting Si(OH).sub.n (OR).sub.4-n are condensed with dehydration to produce a cross-linked product having the unit Si--O--Si which is effective as a dielectric film having an excellent heat resistance. However, due to evaporation and decomposition of ROH upon heating, in addition to evaporation of H.sub.2 O produced from said condensation with dehydration, fine pores are liable to be produced in the SOG layer, and also cracks is liable to occur as a result of progress of curing which can act to clog said pores.
Based on the recognition of the above facts, the formation of an interlayer dielectric layer in semiconductor devices has been further advanced, and particularly, use of organosilicone polymers as an organic dielectric material has been taught in patent and other publications. The organosilicone polymers can be applied with a spin-coater, and accordingly enable the production of a thick dielectric layer having a smooth surface and thus semiconductor devices with a higher yield of production. The prior art organosilicone polymers, however, still suffer from the cracking problem. Moreover, the practically used prior art organosilicone polymers, while they can be spin-coated with smoothing of the layer surface, result in an insufficient smoothing effect, which is not sufficient to accomplish a global planarization in the obtained dielectric layer.
The global planarization will be further described with reference to the accompanying drawings.
FIG. 3 is a cross-sectional view of a semiconductor device having a multilayer or multilevel metallization (three-level metallization) structure in which a silicon substrate 1 has applied thereto three metal layers 2, 12 and 22. Aluminum is used herein as the metal. As is illustrated, the metal layers 2 and 12 are separated from each other through an interlayer dielectric layer 3 and wiring or electrodes of these layers are interconnected through the aluminum filled in a via-hole formed between the layers 2 and 12. Similarly, an interlayer dielectric layer 13 is sandwiched between two metal (Al) layers 12 and 22. A protective layer 23 having a dielectric property as in the dielectric layers 3 and 13 is disposed over the metal layer 22. In the illustrated semiconductor device, each of the dielectric layers 3 and 13 must be globally planarized, i.e., must have a global flat surface, so that the next metal layer can be formed over the dielectric layer without any difficulties.
According to the prior art methods, discussed above, it is difficult to accomplish a global planarization in the multilevel metallization structure. Referring to FIG. 1, it illustrates a cross-sectional view of a prior art semiconductor device having a defective dielectric layer. A patterned metal layer 2 formed over a silicon substrate 1 has two types of patterned steps, i.e., a relatively wide step 2a such as an electrode and a relatively narrow step 2b such as wiring. After formation of the metal layer 2, a dielectric layer 3 is spin-coated over the metal layer 2 by using the above-mentioned organosilicon polymers. The resulting dielectric layer 3, as illustrated, has an uneven surface due to low step coverage of the organosilicon polymers used as a dielectric material. Note that in the areas having the wide step 2a, the layer thickness of the dielectric layer is substantially the same as in the "space" areas having no electrodes or wiring. Desirably, the resulting dielectric layer should have a smooth or planarized surface over the full area of the underlying metal layer regardless of the presence or absence of steps or patterns therein. In other words, it is desired to practice an improved method of forming an interlayer dielectric layer from an organosilicon polymer which method does not cause a cracking problem and also ensures a global planarization.
The inventors of this application have found that a specified polyorganosilsesquioxane (PMMS) is soluble in an organic solvent, can be admixed with the organic solvent to control the viscosity thereof to a desired level, and accordingly is spin-coatable, and the coated layer of the polyorganosilsesquioxane is useful as an interlayer dielectric layer because it can satisfy the above-mentioned requirements concerning the resistance to cracking, planarization, heat resistance, dielectric property and the like. The polyorganosilsesquioxane can be prepared by hydrolyzing organotrichlorosilane or organotrialkoxysilane as a starting material and then condensing with dehydration. Preparation of polyorganosilsesquioxane and use thereof as an interlayer dielectric layer in semiconductor devices are described in, for example, U.S. Pat. No. 4,670,299, which isclosure is described herein for reference. The newly developed polyorganosilsesquioxane can be advantageously used as an interlayer dielectric layer in the production of semiconductor devices, however, there remains the problem that a satisfactory global planarization cannot be attained.
Further, it is noted that if the above-described organic dielectric materials such as polyimide and silicone resins are used in the formation of an interlayer dielectric layer, the dielectric layer is liable to release gases as a result of oxidation of organic groups contained in the layer-forming material during the oxygen (O.sub.2) plasma processing in the multilevel metallization process. The gas generated in the dielectric layer will result in defective areas in the obtained devices and also the oxidation and thermal decomposition of the dielectric material due to exposure to an elevated temperature of around 400.degree. C. will cause a distortion of the dielectric layer and accordingly cracking therein.
On the other hand, use of inorganic dielectric materials such as silicon dioxide and silicon nitride requires use of an expensive apparatus such as a CVD apparatus provided with a vacuum system. In addition, the use of inorganic materials has the drawback that explosive and toxic materials must be used as a source for deposition.
The combined use as a laminated structure of the organic dielectric materials such as polyimide and polyorganosiloxane resins and inorganic dielectric materials such as silicon dioxide, silicon nitride and phosphosilicate glass has been adopted in the formation of the dielectric layer. Generally, a layer of the organic dielectric material is used as the principal portion of the dielectric layer and a layer of the inorganic dielectric material is applied over the organic dielectric layer as a protective layer from the oxygen plasma processing. However, since each of the dielectric materials used has unavoidable drawbacks, the resulting dielectric layer is not satisfactory for use in semiconductor devices. In fact, it is difficult to avoid damage to the underlying organic layer due to application of an elevated temperature during formation of an inorganic layer with the CVD process.
To avoid oxidation decomposition during the oxygen plasma processing, it is contemplated to use a thin coating of fluorocarbon resins such as Teflon.TM.. However, these resins have the added problem that the resin coating will be decomposed upon thermal treatment in the production process of the semiconductor devices, because the thermal resistance of such resins is not good and on the order of 350.degree. C.
With regard to cracking caused in the interlayer dielectric layer, there is another observation that silicone-type hard coat materials which are also spin-coatable can be used as a dielectric material, and upon curing, can provide a dielectric layer having a low coefficient of thermal expansion similar to that of the silicon oxide layer, however, the dielectric layer, even if it has a notably reduced layer thickness of 5000.ANG. or less, cannot avoid cracking caused by the internal strain of the layer and thermal shock.